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| SL74HC240 Octal 3-State Inverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS The SL74HC240 is identical in pinout to the LS/ALS240. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This octal inverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other busoriented systems. The device has inverting outputs and two active-low output enables. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC240N Plastic SL74HC240D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Enable A, Enable B PIN 20=VCC PIN 10 = GND L L H A,B L H X Outputs YA,YB H L Z X = don't care Z = high impedance SLS System Logic Semiconductor SL74HC240 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 35 75 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HC240 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 0.5 85 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 5.0 125 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 10.0 A A V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V IOUT 20 A VOUT= VCC-0.1 V IOUT 20 A VIN= VIL IOUT 20 A VIN=VIL IOUT 6.0 mA IOUT 7.8 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN=VIH IOUT 20 A VIN= VIH IOUT 6.0 mA IOUT 7.8 mA IIN IOZ Maximum Input Leakage Current Maximum three State Leakage Current VIN=VCC or GND Output in High-Impedance State VIN = VIL or VIH VOUT=VCC or GND VIN=VCC or GND IOUT=0A ICC Maximum Quiescent Supply Current (per Package) 6.0 4.0 40 160 A SLS System Logic Semiconductor SL74HC240 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3) Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 3) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Transceiver Channel) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 80 16 14 110 22 19 110 22 19 60 12 10 10 15 85C 100 20 17 140 28 24 140 28 24 75 15 13 10 15 125C 120 24 20 165 33 28 165 33 28 90 18 15 10 15 Unit ns tPLZ, t PHZ ns tPZH, t PZL ns tTLH, t THL ns CIN COUT pF pF Typical @25C,VCC=5.0 V 32 pF Figure 1. Switching Waveforms Figure 2. Switching Waveforms SLS System Logic Semiconductor SL74HC240 Figure 3. Test Circuit Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM (1/8 of the Device) SLS System Logic Semiconductor |
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